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DESIGNING AN EFFICIENT APPROACH FOR JK AND TFlip-FLOP WITH POWER DISSIPATION ANALYSIS USING QCA
Pandey, Shraddha and Singh, Sonali and Wairya, Subodh
Int J VLSI Des Commun Syst
2016
3
7
29–48
Output
No Output!
Affiliations
No Affiliations!
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